1. Field of Invention
The invention relates to a fabrication method of semiconductor devices and, in particular, to a fabrication method of semiconductor devices that employs ion implantation to modulate the stress on a silicon nitride film in the semiconductor device.
2. Related Art
For a P-type metal oxide semiconductor (PMOS), the hole mobility can be improved by imposing a compressive stress in the channel region. On the other hand, for an N-type metal oxide semiconductor (NMOS), the electron mobility can be improved by imposing a tensile stress in the channel region. The stresses required to improve the carrier mobility in the channel region in these two types of transistors are opposite to each other.
Since the stress value and type of depositing a whole piece of silicon nitride film are fixed, therefore, one can only choose one of the PMOS and NMOS to impose the required stress in the prior art. That is, one can only improve one type of devices at a time, but not both of them simultaneously.
There have been many ion implantation technologies disclosed to improve the layer stress in silicon nitride. For example, the U.S. Pat. No. 6,146,972 proposed a method that employs ion implantation to implant ions at 20% to 60% of the silicon nitride film to reduce the stress therein. Its dose is smaller than 1×1015cm−2 to prevent defects on the lower silicon plate under the stress of the silicon nitride.
Besides, A. Shimizu, K. Hachimine et al. implant Ge into the silicon nitride film to release the stress in a certain region. For example, to improve the characteristics of PMOS, a silicon nitride film with a high compressive stress is deposited on the transistor as a cap layer. The stress in the silicon nitride film on the NMOS region on the same substrate is released using Ge implantation to prevent the desired NMOS characteristics from being changed. The opposite is performed if one wants to improve the NMOS characteristics.
Therefore, the prior art has not addressed and answered the question of how to simultaneously provide different stresses on different devices on the same wafer. Since a CMOS contains both PMOS and NMOS devices, it is thus imperative to provide a method that enables a silicon nitride film to present different stresses in different regions.